MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 116
MC68HC908JG16FA
Manufacturer Part Number
MC68HC908JG16FA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JG16FA.pdf
(324 pages)
- Current page: 116 of 324
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System Integration Module (SIM)
Technical Data
116
INT/BREAK
OSCDCLK
IAB
NOTE:
Figure 8-19. Stop Mode Recovery from Interrupt or Break
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
Freescale Semiconductor, Inc.
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction
For More Information On This Product,
STOP +1
R/W
IAB
IDB
System Integration Module (SIM)
Go to: www.freescale.com
STOP ADDR
Figure 8-18. Stop Mode Entry Timing
Figure 8-18
STOP + 2
PREVIOUS DATA
STOP RECOVERY PERIOD
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
SP – 1
SAME
MC68HC908JG16
SAME
SP – 2
SAME
SP – 3
MOTOROLA
SAME
—
Rev. 1.0
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