MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 256
MC68HC908JG16FA
Manufacturer Part Number
MC68HC908JG16FA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JG16FA.pdf
(324 pages)
- Current page: 256 of 324
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Input/Output (I/O) Ports
Technical Data
256
* DDRA7 bit is reset by POR or LVI reset only.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
Data Direction Register C
Data Direction Register D
Data Direction Register A
Data Direction Register B
Register Name
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Port E Data Register
NOTE:
(DDRC)
(DDRD)
(DDRA)
(DDRB)
(PTC)
(PTD)
(PTA)
(PTB)
(PTE)
Connect any unused I/O pins to an appropriate logic level, either V
V
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
SS
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 14-1. I/O Port Register Summary
Freescale Semiconductor, Inc.
. Although the I/O ports do not require termination for proper
For More Information On This Product,
DDRA7
PTA7
Bit 7
0*
0
0
0
0
0
0
0
0
0
0
Go to: www.freescale.com
Input/Output (I/O) Ports
= Unimplemented
DDRA6
PTA6
6
0
0
0
0
0
0
0
0
0
0
0
DDRA5
DDRD5
PTA5
PTD5
5
0
0
0
0
0
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
DDRA4
DDRD4
Unaffected by reset
PTA4
PTD4
PTE4
4
0
0
0
0
0
0
0
0
DDRA3
DDRD3
PTA3
PTD3
PTE3
3
0
0
0
0
0
0
0
0
MC68HC908JG16
DDRD2
DDRA2
PTD2
PTA2
PTE2
2
0
0
0
0
0
0
0
0
DDRC1
DDRD1
DDRA1
PTC1
PTD1
PTA1
PTE1
1
0
0
0
0
0
0
MOTOROLA
—
Rev. 1.0
DDRA0
DDRB0
DDRC0
DDRD0
PTA0
PTB0
PTC0
PTD0
PTE0
DD
Bit 0
0
0
0
0
or
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