MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 125

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908JG16
MOTOROLA
—
Rev. 1.0
If V
(Table 9-1
clock, f
entry
the external clock. Holding the PTA3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if
V
the OSCDCLK frequency.
Entering monitor mode with V
as V
Integration Module (SIM)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTA3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
TST
Freescale Semiconductor, Inc.
TST
TST
For More Information On This Product,
is applied to IRQ. In this event, the OSCOUT frequency is equal to
(Table 9-1
Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart
XCLK
is applied to IRQ and PTA3 is low upon monitor mode entry
is applied to either the IRQ or the RST. (See
condition set 1), the bus frequency is a equal to the external
. If PTA3 is high with V
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Monitor ROM (MON)
condition set 2), the bus frequency is a divide-by-two of
DD
), then all port A pin requirements and conditions,
MONITOR MODE
TRIGGERED?
POR RESET
IS VECTOR
EXECUTE
MONITOR
BLANK?
CODE
for more information on modes of operation.)
POR
YES
YES
TST
(Table 9-1
TST
on IRQ, the COP is disabled as long
NO
NO
applied to IRQ upon monitor mode
condition set 3, where IRQ
NORMAL USER
MODE
Section 8. System
Functional Description
Monitor ROM (MON)
Technical Data
125