MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 71
MC68HC908JG16FA
Manufacturer Part Number
MC68HC908JG16FA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JG16FA.pdf
(324 pages)
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MC68HC908JG16
MOTOROLA
NOTE:
—
Rev. 1.0
SSREC — Short Stop Recovery Bit
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
SSREC enables the CPU to exit stop mode with a delay of 2048
OSCDCLK cycles instead of a 4096 OSCDCLK cycle delay.
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 17. Computer Operating Properly
STOP enables the STOP instruction.
COPD disables the COP module. (See
Operating Properly
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Stop mode recovery after 2048 OSCDCLK cycles
0 = Stop mode recovery after 4096 OSCDCLK cycles
1 = COP timeout period is 2
0 = COP timeout period is 2
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Configuration Register (CONFIG)
Go to: www.freescale.com
(COP).)
13
18
– 2
– 2
4
4
OSCDCLK cycles
OSCDCLK cycles
Section 17. Computer
Configuration Register (CONFIG)
(COP).)
Configuration Register
Technical Data
71
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