MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 99

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

8.3.1 Bus Timing
8.3.2 Clock Startup from POR or LVI Reset
8.3.3 Clocks in Stop Mode and Wait Mode
8.4 Reset and System Initialization
MC68HC908JG16
MOTOROLA
—
Rev. 1.0
In user mode, the internal bus frequency is the oscillator frequency
divided by two.
When the power-on reset (POR) module or the low-voltage inhibit
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 OSCDCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
OSCDCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 2048 OSCDCLK cycles. (See
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
The MCU has the following reset sources:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Illegal opcode
Illegal address
Universal serial bus module (USB)
Low-voltage inhibit module (LVI)
System Integration Module (SIM)
Go to: www.freescale.com
System Integration Module (SIM)
Reset and System Initialization
8.7.2 Stop
Technical Data
Mode.)
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