MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 267

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

14.6.2 Data Direction Register D
MC68HC908JG16
MOTOROLA
NOTE:
NOTE:
—
Rev. 1.0
Address:
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[5:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
For those devices packaged in a 32-pin low-profile quad flat pack,
PTD5–4 are not connected. DDRD5–4 should be set to a 1 to configure
PTD5–4 as outputs.
Figure 14-13
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[5:0], configuring all port D pins as inputs.
Port D pins are open-drain when configured as output.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
$0007
Bit 7
Figure 14-12. Data Direction Register D (DDRD)
0
0
Go to: www.freescale.com
shows the port D I/O circuit logic.
Input/Output (I/O) Ports
6
0
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
DDRD2
2
0
Input/Output (I/O) Ports
DDRD1
1
0
Technical Data
DDRD0
Bit 0
Port D
0
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