PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 10

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 1-8. PCI IP Core Quick Facts--PCI target 33MHz/32bit
Features
• Available as 32/64-bit PCI bus and 32/64-bit local bus
• PCI SIG Local Bus Specification, Revision 3.0 compliant
• 64-bit addressing support (dual address cycle)
• Capabilities list pointer support
• Parity error detection
• Up to six Base Address Registers (BARs)
• Fast back-to-back transaction support
• Supports zero wait state transactions
• Special cycle transaction support
• Customizable configuration space
• Up to 66MHz PCI
• Fully synchronous design
Core 
Require-
ments
Resource 
Utiliza-
tion
Design
Tool Sup-
port
FPGA
Families
Supported
Minimal
Device
Needed
Data Path
Width
LUTs
Registers
Lattice
Implemen-
tation
Synthesis
Simulation
LCMXO1200
E-5FT256C
MachXO
6TG144CES
MachXO2
LCMXO-
1200HC-
Synopsys Synplify Pro for Lattice D-2009.12L-1
LatticeECP
LatticeEC
LFEC3E-
5Q208C
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Mentor Graphics Precision RTL
Diamond 1.0 or ispLEVER 8.1
10
PCI target 33MHz 32bit
PCI IP configuration
LFE2-6E-
ECP2M
6F256C
Lattice
Lattice
ECP2
600
500
32
LatticeXP
LFXP3C-
5Q208C
LatticeXP2
LFXP2-5E-
6QN208C
PCI IP Core User’s Guide
7FTN256CES
LatticeXP3
LFE3-17EA-
Introduction
LatticeSCM
LFSC3GA15
LatticeSC
E-6F256C