PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 11

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

IPUG18_09.2, November 2010
This chapter provides a functional description of the Lattice PCI IP core.
The PCI IP cores bridge the PCI bus to the back-end application. They decode transactions and pass PCI requests
to the Local Interface. The back-end applications then send or receive the proper data associated with the PCI
Interface via their Local Interface to respond to the PCI transactions. In the case of master versions the core exe-
cutes PCI bus transactions based on back-end requests.
bus structure used in the PCI IP core.
Block Diagram
Figure 2-1. PCI IP core Block Diagram
The PCI Master Target IP Core consists of multiple blocks, as shown in
description of these blocks.
PCI Master Control
The PCI Master Control interfaces with the PCI bus. It supports all of the address and command signals required to
execute transactions on the PCI bus for both 32-bit and 64-bit PCI applications. A list of the supported PCI signals
is available in the PCI Interface Signals section of this document. Once the Local Master Interface Control is
granted the bus, it passes the transaction information to the PCI Master Control using the internal bus. The PCI
Master Control then requests and executes the transaction on the PCI bus. The PCI IP cores support all of the
Arbitration
Reporting
Extension
Interface
Address
Interrupt
Control
System
& Data
64-Bit
Error
cben[3:0]
ad[63:32]
cben[7:4]
ad[31:0]
devseln
ack64n
framen
req64n
par64
stopn
perrn
serrn
trdyn
irdyn
intan
idsel
reqn
gntn
rstn
par
clk
Interface
PCI
Note: Signals in shaded boxes are used for 64-bit PCI Cores.
Generator
Checker
Control
Control
Master
Target
Parity
and
PCI
PCI
Configuration
Space
11
Figure 2-1
Interface
Interface
Control
Master
Control
Target
Local
Local
Functional Description
illustrates the functional modules and internal
Figure
Interface
Local
2-1. This section provides a detailed
lm_burst_length[11:0]
lm_data_xfern
lm_rdyn
lm_status[3:0]
command[9:0]
status[5:0]
cache[7:0]
lt_address_out[31:0]
l_ad_in[31:0]
l_data_out[31:0]
lt_cben_out[3:0 ]
lt_command_out[3:0 ]
lm_cben_in[3:0]
lt_address_out[63:32]
lt_cben_out[7:4]
lt_ldata_xfern
lt_64bit_transn
lm_64bit_transn
lm_hdata_xfern
lm_ldata_xfern
lm_cben_in[7:4]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_r_nw
lm_timeoutn
lm_abortn
lm_req32n
lm_req64n
lm_gntn
lt_r_nw
lt_abortn
lt_disconnectn
lt_rdyn
lt_data_xfern
lt_accessn
l_Interruptn
bar_hit[5:0]
exprom_hit
new_cap_hit
l_ad_in[63:32]
l_data_out[63:32]
lt_hdata_xfern
PCI IP Core User’s Guide
Configuration
space port
[401:0]
Extension
Register
Interface
Interface
Interrupt
Address
Decode
Control
Control
& Data
Master
Master
req/gnt
Config
Target
64-Bit
Chapter 2: