PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 138

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Local Data Bus Size (Target cores only)
The data width for Local side Target read/write transactions, must be the same as the PCI Data Bus Size.
Local Address Bus Width
The address width for Local Master and Target read/write transactions, must be the same as the PCI Data Bus
Size.
Bus Speed
PCI bus operation frequency. A clock frequency on the PCI side. A fixed value that depends on the PCI core being
used.
Backend Configuration
Enable Backend Configuration
When this option is selected, the core works independently by configuring in the backend. The PCI core will provide
a backend interface named self_cfg. The self_cfg interface can directly configure the PCI core after power on
instead of another PCI master on PCI bus. The self_cfg interface can read/write the PCI core configuration space.,
The core takes the read/write command same as PCI config command(cben=h02/h03).
The self_cfg interface signals are listed in
Table 3-2. self_cfg Interface Signals
The backend asserst self_cfn_en to '1' and then starts configuring the PCI core. After configuration is finished,
self_cfg_en is deasserted to '0'.
Synthesis/Simulation Tools Selection
Support Synplify
If selected, IPexpress generates evaluation scripts and other associated files required to synthesize the top-level
design using the Synplify synthesis tool.
Support Precision
If selected, IPexpress generates evaluation script and other associated files required to synthesize the top-level
design using the Precision synthesis tool.
Support ModelSim
If selected, IPexpress generates evaluation script and other associated files required to synthesize the top-level
design using the Modelsim simulator.
Support ALDEC
If selected, IPexpress generates evaluation script and other associated files required to synthesize the top-level
design using the ALDEC simulator.
self_cfg_en
self_cfg_addr
self_cfg_data_in
self_cfg_data_out
self_cfg_rd_wrn
self_cfg_rdy
Port Name
Type
Out
Out
In
In
In
In
ad (address cycle)
ad (data cycle of config write command)
ad (data cycle of config read command)
cben(0)
!delseln & !trdyn
Corresponding PCI signals
Table
3-2.
138
Self configuration enable signals, when it’s 1’b1,
pci bus will be blocked and replaced by self_cfg
interface.
Address of configuration space
Data write to configuration space
Data read from configuration space
Specify the Read/write command. ‘1’ define a read
command, ‘0’ define a write command.
Only valid for read command, ‘1’ indicate that
self_cfg_data_out is valid.
Description
PCI IP Core User’s Guide
Parameter Settings