PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 20

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-5. Command Register Description
IPUG18_09.2, November 2010
Figure 2-3. Command Register
Location
10-15
Bit
0
1
2
3
4
5
6
7
8
9
I/O Space Enable controls a device’s response to I/O space accesses. I/O space accesses are enabled if the bit
is set to a 1. After reset the I/O space enable bit is set to a 0.
Memory Space Enable controls a device’s response to memory space accesses. Memory space accesses are
enabled if the bit is set to a 1. After reset the memory space enable bit is set to a 0.
Bus Master enables the PCI IP core to act as a master on the PCI bus when this bit is set to 1. After reset the Bus
Master enable bit is set to a 0.
Special Cycle controls a device’s action on special cycle operations. Special cycle accesses are enabled if the bit
is set to 1. After reset the bit is set to 0.
Memory Write and Invalidate Enable controls the PCI IP core's ability to execute the Memory Write and Invali-
date cycle on the PCI bus. The Core, when required, will issue the Memory Write and Invalidate command if this
bit is set to a 1. After reset this bit is set to a 0.
VGA Palette Snoop
Parity Error Response is used to control a device’s response to parity errors. If the bit is 0, a parity error causes
the Detected Parity Error status bit to be set in the status register but does not drive the perrn signal. After reset
the bit is set to 0. This is the enable for parity error checking. However, even with the perrn signal disabled, the
device is still required to generate parity.
Reserved Bit
SERR Enable is used to enable the serrn driver. To enable, this bit is set to a 1. After reset this bit is set to 0.
Fast Back-to-Back Enable allows the PCI IP core to execute fast back-to-back transactions to different devices. If
the fast back-to-back enable is set to a 1, the Core executes fast back-to-back transactions. After reset this bit is
set to 0.
Reserved Bits The returned value for these bits is 0 when this register is read.
Fast Back-to-Back Enable
SERR# Enable
Reserved Bit
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate Enable
Special Cycle
Bus Master
Memory Space Enable
I/O Space Enable
15
10
9
20
Description
8
7
6
5
4
3
2
Functional Description
1
PCI IP Core User’s Guide
0