PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 53

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-19. 32-bit Master Burst Read Transaction with a 32-bit Local Interface (Continued)
CLK
10
6
7
8
9
Turn around
Address
Phase
Data 1
Data 2
Data 3
The Core asserts framen to start transaction and the local master de-asserts lm_req32n when
the previous lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request another
PCI bus transaction.
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[3:0]. Asserting lm_rdyn also
means the local master is ready to read data. If it is not ready to read data, it keeps lm_rdyn de-
asserted until it is ready.
The Core de-asserts reqn when framen was asserted but lm_req32n was de-asserted on the
previous cycle.
The Core tri-states the ad[31:0] lines and drives the byte enables (Byte Enable 1). Since
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read data.
Because the Core performs the burst transactions, it keeps framen asserted.
It de-asserts lm_gntn to follow gntn.
The target asserts trdyn and puts Data 1 on ad[31:0].
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the local master is ready to read the first DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 2 on
l_data_out[31:0] and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern the local master to signify Data 1 are available on l_data_out[31:0]. With
lm_data_xfern asserted, the local master can safely read Data 1 and increment the address
counter.
If the local master keeps lm_rdyn asserted on the previous cycle, the Core keeps irdyn
asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next DWORD
(Data 2) on ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 3 on
l_data_out[31:0] and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 2 are available on l_data_out[31:0].
With lm_data_xfern asserted, the local master can safely read Data 2 and increment the
address counter.
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
Because the current transaction is the last, the master de-asserts framen to signal the end of the
burst.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next DWORD
(Data 3) on ad[31:0]. If the local master is ready to read the next DWORD, it keeps lm_rdyn
asserted.
Since both irdyn and trdyn are asserted, the third data phase is completed on this cycle.
53
Description
Functional Description
PCI IP Core User’s Guide