PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 24

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Capabilities Pointer
The Capabilities Pointer indicates the starting location of the Capabilities List. It resides at address location 34h.
The Capabilities Pointer consists of an 8-bit read-only register location. The capabilities pointer must be enabled by
the CAP_PTR_ENA parameter. The CAP_POINTER parameter determines the value of this register.
Min_Gnt
The Min_Gnt read-only register is an 8-bit field that is used to specify the length of time in microseconds for the
Master to control the PCI bus. It resides in the upper 8 bits of address location 3Ch. The MIN_GRANT parameter
determines the value of this register.
Max_Lat
The Max_Lat read-only register is an 8-bit field that is used to specify the how often the PCI IP core the bus. It
resides in the third byte of address location 3Ch. The MAX_LATENCY parameter determines the value of this regis-
ter.
Interrupt Line
The Interrupt Line register is set by the interrupt handling mechanism to define the interrupt routing. This is a
read/write register is handled outside the operation of the PCI IP core. This register holds system interrupt routing
information.
Interrupt Pin
The Interrupt Pin register is used to indicate which of the four interrupts that the PCI IP core uses. Because the PCI
IP core is a single function device, the only Interrupt Pin that can be selected is Interrupt A. If the interrupt is
selected, the INTERRUPT_PIN parameter sets the register with a value of 01h. This eight-bit register is located at
address location 3Dh.
Reserved
All reserved registers are read-only. Write operations to reserved registers are completed normally, and the data is
discarded. A 0 is returned after the read operations to reserved registers are completed normally.
Lattice PCI IP core Configuration Options
Lattice PCI IP core allows an extensive definition of the PCI Configuration Space for optimum performance.
IPexpress User-Controlled Configurations
The IPexpress user-configurable flow provides evaluation capability for any valid combination of parameters. Con-
figurations can have a maximum of three BARs. To create a configuration with more than three BARs, contact Lat-
tice.
The evaluation configurations of PCI IP core have a maximum of three BARs. To order a configuration with more
than three BARs, contact Lattice.
Table 2-9. IPexpress Parameters for PCI IP Core
Number of BARs
Bus Definition Parameters
PCI Data Bus Size
Local Master Data Bus Size
Local Target Data Bus Size
Parameter Name
32- or 64-bit
32- or 64-bit
32- or 64-bit
Range
1-6
24
Functional Description
PCI IP Core User’s Guide
Default(s)
Note 1
Note 2
Note 2
3