PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 132

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-49
Figure 2-49. 32-bit Target Retry for Write Transaction
Table 2-55. 32-bit Target Retry for Write Transaction
CLK
4
5
6
7
l_data_out[31:0]
lt_disconnectn
lt_addressout
lt_data_xfern
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
lt_r_nw
framen
lt_rdyn
and
stopn
trdyn
irdyn
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal remains high to indicate that the back-end application is not ready to provide data. Because the target can
not complete any PCI data phases, the lt_rdyn signal remains high and the lt_disconnectn signal is
driven low.
The lt_data_xfern signal remains high because the lt_rdyn signal was high during the previous cycle.
The stopn signal is driven low on the PCI bus as the lt_disconnectn signal was driven low for the previous
two clock cycles.
The PCI master de-asserts the framen to acknowledge the retry initiated by the target.
par
clk
Table 2-55
1
Don’t care
Command
Address
Bus
0x00
show a Retry on a write transaction.
2
Address
Parity
3
Byte Enable 1
4
Data 1
Data Parity 1
5
132
Don’t care
Description
0x01
6
Address
Don’t care
Don’t care
7
Don’t care
8
Functional Description
PCI IP Core User’s Guide
9
0x00
10