PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 74

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-22. 32-Bit Master Dual Address Cycle – Write Transaction
Table 2-26. 32-bit Master Dual Address Cycle – Write Transaction
CLK
1
2
3
4
Phase
Idle
Idle
Idle
Idle
lt_command_out[3:0]
The lm_req32n signal is asserted by the local master to request for 32-bit data transaction. The
local master issues the PCI starting address, the bus command (DAC), and the burst length during
the same clock cycle on l_ad_in, lm_cben_in and lm_burst_length, respectively.
The Core’s Local Master Interface detects the asserted lm_req32n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
lt_cben_out[3:0]
lt_cben_out[7:4]
lt_64bit_transn
lt_address_out
lt_hdata_xfern
l_ad_in[63:32]
lt_ldata_xfern
l_ad_in[31:0]
bar_hit[5:0]
lt_accessn
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
devseln
ack64n
lt_r_nw
framen
req64n
lt_rdyn
par64
trdyn
irdyn
par
clk
1
Don't care
Don't care
Don't care
Don't care
Command
Address
Bus
Don't care
Don't care
0x00
2
Don't care
Address
Parity
Don't care
Don't care
3
4
74
Byte Enable 1
Byte Enable 2
Don't care
Don't care
5
Bus Command
Byte Enable 1
Byte Enable 2
Don't care
Don't care
Description
Address
Data 1
Data 2
0x01
6
Data 1
Data 2
7
Don't care
Don't care
Parity 1
Parity 2
Data
Data
8
Don't care
Don't care
0x00
Functional Description
9
PCI IP Core User’s Guide