PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 18

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
PCI Configuration Space Setup
Determining the correct settings for the Configuration Space is an essential step in designing a PCI application,
because the device may not function properly if the Configuration Space is not properly configured. The PCI IP
core supports all of the required and some additional Configuration Space registers that apply to the PCI IP core
(refer to PCI Local Bus Specifications, Revision 3.0, Chapter 6).
Space for the PCI IP core. This section describes the first 64 bytes of the Configuration Space in the PCI IP core
and its customization method. For more information on the parameters used to customize the Configuration Space,
refer to the Lattice PCI IP core Configuration Options section.
Table 2-4. Local Interface Signals
lm_status[3:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
1. Shaded rows apply to 64-bit applications.
2. A Memory Write and Invalidate transaction is not governed by the Latency Timer except at cacheline boundaries. A master that initiates a
3. During Master Read operation the signal lm_data_xfern always reflects valid data in the local data bus. But during Master Write opera-
transaction with the Memory Write and Invalidate command ignores the Latency Timer until a cacheline boundary. When the Latency Timer
has expired (and gntn is deasserted), the core asserts lm_timeoutn. The backend must terminate the transaction at next cacheline
boundary by asserting lm_abort.
tion, due to data prefetch ahead of the transactions on PCI bus, lm_data_xfern along with the lm_status reflects the data validity. If
lm_status is 0100, (meaning a Bus Termination) ignore the lm_data_xfern assertion because the data being prefetched is not sent
out on the PCI bus due to termination.
Name
out
out
out
I/O
1
Polarity
(Continued)
—
—
—
Indicate the master operation status.
0001 - Address loading
0010 - Bus transaction
0100 - Bus termination
1000 - Fast_back_to_back
Indicate the master termination status.
000 - Normal termination
Normal termination occurs when the master finishes and completes the
transaction normally. During a multi-data phase transfer, a condition can
occur where the master’s latency timer expires on the last data phase and
master's gntn has been de-asserted. In this case, lm_timeoutn is
asserted and the master also indicates this as Normal termination.
001 - Timeout termination
Timeout termination occurs when, during a multi-data phase transfer, the
master’s latency timer expired before the last data phase and the master’s
gntn is de-asserted on or before the last data phase. lm_timeoutn is also
asserted in this case.
010 - No target response termination.
This is also known as Master Abort termination.
011 - Target abort termination
100 - Retry termination
101 - Disconnect data termination
110 - Grant abort termination
111 - Local master termination
Local master burst transaction “down counter” value. When the local master
requests a 32-bit transaction, the initial value of lm_burst_cnt is equal to
lm_burst_length. When the local master requests a 64-bit transaction
and lm_64bit_transn is active, the initial value of lm_burst_cnt is
equal to lm_burst_length. When the local master requests a 64-bit
transaction and lm_64bit_transn is inactive, the initial value of
lm_burst_cnt is double of lm_burst_length.
18
Figure 2-2
Description
shows the supported Configuration
Functional Description
PCI IP Core User’s Guide