PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 159

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
MachXO FPGAs
Table A-13. Performance and Resource Utilization
Ordering Part Number
Table A-14
MachXO.
Table A-14. MachXO OPN for PCI IP Core
MachXO2 FPGAs
Table A-15. Performance and Resource Utilization
Ordering Part Number
Table A-16
MachXO2.
Table A-16. OPN for MachXO2 PCI IP Core
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Target 66 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LCMXO2280C-5FT324C device with Lattice Diamond 1.0 software. Performance
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LCMXO2-1200HC-6TG144CES device with Lattice Diamond 1.0 software. Perfor-
may vary when using a different software version or targeting a different device density or speed grade within the MachXO family.
mance may vary when using a different software version or targeting a different device density or speed grade within the MachXO2 family.
User-Configurable Mode
User-Configurable Mode
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for
IPexpress
IPexpress
33 MHz
66 MHz
33 MHz
33 MHz
33 MHz
Speed
Speed
PCI Bus
PCI Bus
32-bit
32-bit
32-bit
32-bit
32-bit
SLICEs
SLICEs
359
517
542
304
406
Master/Target
Master/Target
LUTs
LUTs
1060
703
966
601
803
1
1
Target
Target
Target
Type
Type
159
Registers
Registers
472
493
642
422
582
PCI-MT32-XO-U6
PCI-MT32-M2-U1
PCI-T32-XO-U6
PCI-T32-XO-U6
PCI-T32-M2-U1
sysMEM
sysMEM
EBRs
EBRs
OPN
OPN
0
0
0
0
0
(PCI Interface)
(PCI Interface)
External Pins
External Pins
Resource Utilization
PCI IP Core User’s Guide
48
48
50
48
50
f
f
MAX
MAX
33
66
33
33
33