PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 160

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
LatticeSC FPGAs
Table A-17. Performance and Resource Utilization
Ordering Part Number
Table A-18
ticeSC.
Table A-18. OPN for LatticeSC PCI IP Core
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Target 33 MHz, 64-bit PCI/
Local/Address bus width
Target 66 MHz, 32-bit PCI/
Local/Address bus width
Target 66 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 64-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LFSC3GA25E-6F900C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC family.
User-Configurable Mode
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for Lat-
IPexpress
33 MHz
33 MHz
66 MHz
66 MHz
33 MHz
33 MHz
66 MHz
66 MHz
Speed
PCI Bus
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
SLICEs
1085
1513
488
621
618
845
724
986
Master/Target
Master/Target
Master/Target
Master/Target
LUTs
1391
1050
1529
1722
2631
1
679
893
990
Target
Target
Target
Target
Type
160
Registers
470
594
493
622
640
850
663
871
PCI-MT32-SC-U6
PCI-MT64-SC-U6
PCI-MT32-SC-U6
PCI-MT64-SC-U6
PCI-T32-SC-U6
PCI-T64-SC-U6
PCI-T32-SC-U6
PCI-T64-SC-U6
sysMEM
EBRs
OPN
0
0
0
0
0
0
0
0
(PCI Interface)
External Pins
Resource Utilization
PCI IP Core User’s Guide
48
87
48
87
50
89
50
89
f
MAX
33
33
66
66
33
33
66
66