PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 123

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-48. Advanced Configuration Write Transaction
Target Termination
The back-end application has full control over the termination of all PCI transactions requesting information from
the Local Interface. The back-end application must handle the termination properly. The four types of target-initi-
ated termination are:
• Retry
• Target Abort
• Disconnect With Data
• Disconnect Without Data
The back-end application utilizes the Local Interface signals lt_abortn, lt_disconnectn, and lt_rdyn to ini-
tiate termination. These signals control the target’s response and termination of PCI transactions that request data
from the Local Interface.
In order to prevent a PCI IP core from monopolizing the PCI bus, the PCI Local Bus Specification, Revision 3.0
includes limitations on the amount of transferring time for a target. During the initial data phase, the target must
issue a Retry if it cannot respond within 16 clocks of framen being asserted. For subsequent data phases follow-
ing the initial data phase, the PCI IP core must respond within eight clock cycles or issue a Disconnect Without
Data or a Target Abort. The first option is preferred. The different target initiated termination sequences are dis-
cussed in the following section.
CLK
1
2
3
4
5
6
7
Turn around
PCI Data
Address
Phase
Data 1
Wait
Wait
Wait
Idle
Table 2-49
The master asserts framen and idsel. It and drives the configuration address on ad[31:0] and
the read command on cben[3:0].
The PCI master drives the first byte enables (Byte Enable 1) on cben[3:0]. If it is ready to write
data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].The Core starts to
decode the address and command.
If there is an address match, the Core drives the new_cap_hit signals to the back-end. The
back-end can use new_cap_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after
new_cap_hit. If the back-end is ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of
framen, ad[31:0] and cben[3:0]. It also de-asserts irdyn if both trdyn and irdyn were
asserted last cycle.
It de-asserts both devseln and trdyn if both trdyn and irdyn were asserted last cycle.
The Core signals to the back-end that the transaction is complete by clearing new_cap_hit. It
also de-asserts lt_data_xfern.
The Core relinquishes devseln and trdyn.
shows a summary of the different target initiated termination types.
123
Description
Functional Description
PCI IP Core User’s Guide