PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 103

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-35
select timing is set to slow and wait states are not inserted. The figure illustrates how the PCI interface correlates to
the Local Target Interface. The table gives a clock-by-clock description of each event that occurs in the figure.
Figure 2-35. 32-bit Target Burst Write Transaction with a 32-bit Local Interface
lt_command_out[3:0]
l_data_out[31:0]
lt_cben_out[3:0]
lt_address_out
lt_data_xfern
bar_hit[5:0]
and
lt_access
cben[3:0]
ad[31:0]
devseln
lt_r_nw
framen
lt_rdyn
trdyn
irdyn
par
clk
Table 2-40
1
Don’t care
Don’t care
Command
Address
Bus
Don’t care
show an example of a 32-bit burst write transaction. The assumption is that the device
0x00
2
Address
Parity
3
Don’t care
Byte Enable 1
4
Data 1
Byte Enable 1
Data Parity 1
103
5
Bus Command
Address
6
0x01
Enable 2
Data 2
Data 1
Byte
7
Enable 3
Enable 2
Parity 2
Data 3
Data 2
Byte
Byte
Data
8
Functional Description
Enable 3
Parity 3
Data 3
Byte
Data
PCI IP Core User’s Guide
9
Don’t care
Don’t care
0x00
10