PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 48

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-17. 32-bit Master Read Transaction with Local Wait State (Continued)
IPUG18_09.2, November 2010
CLK
10
11
12
13
6
7
8
9
Turn around
Turn around
Master Wait
PCI Data
Address
Phase
Data 1
Data 2
Data 3
Idle
the local master provides the byte enables on lm_cben_in[3:0]. Asserting lm_rdyn also
means the local master is ready to read data. If it is not ready to read data, it keep lm_rdyn de-
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read data.
Because this is not the last cycle transaction, the Core keeps framen.
The target asserts devseln to response the command.
The Core de-asserts lm_gntn to follow gntn.
With the trdyn asserted, Data 1 is driven on to ad[31:0]. If the PCI IP core is ready to receive
data, irdyn remains asserted and it keeps the Byte Enables on cben[3:0].
The Local Master interface is ready to receive data, so it keeps lm_rdyn.
If the PCI IP core is ready to receive data, it asserts irdyn and keeps the byte enables on
cben[3:0]. The target device drives Data 2 on the PCI bus.
Since the previous data phase was completed, the master transfers Data 1 on
l_data_out[31:0] and decreases lm_burst_cnt to two. The Core asserts lm_data_xfern
if lm_rdyn was asserted on the previous cycle.
The local master interface is not ready to receive next data, so it de-asserts lm_rdyn.
asserted on the previous cycle. The local master asserts lm_rdyn for being ready to receive data.
The Core de-asserts idyn, the target de-asserts both devseln and trdyn. The Core relin-
quishes control of framen, ad[31:0], and cben[3:0]. Since the previous data phase was com-
pleted, the Core transfers Data 1 on l_data_out[31:0] and decreases lm_burst_cnt to
zero. The Core asserts lm_data_xfern if lm_rdyn was asserted on the previous cycle.
The Core changes lm_status[3:0] into the ‘Bus Termination’ state with lm_termination as
‘Normal Termination’ because both trdyn and irdyn were asserted last cycle.
The Core relinquishes control of irdyn.
The Core asserts framen to start transaction and the local master de-asserts lm_req32n when
the previous lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request another
PCI bus transaction.
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
asserted until it is ready.
The Core de-asserts reqn when framen was asserted and lm_req32n was de-asserted on the
previous cycle.
The Core tri-states the ad[31:0] lines and drives the byte enables (Byte Enable 1). Since
Since lm_rdyn was de-asserted on the previous cycle, the Core de-asserts irdyn to signify the
Core is inserting a wait state. The target device drives Data 3 on the PCI bus.
Since the previous data phase was completed, the Core transfers Data 2 on l_data_out[31:0]
and decreases lm_burst_cnt to one. The Core de-asserts lm_data_xfern if lm_rdyn wasn’t
asserted on the previous cycle.
The local master asserts lm_rdyn for being ready to receive data.
The Core asserts irdyn and de-asserts framen for the last data phase. The target keeps
devseln, trdyn and Data 3 on PCI bus. The Core asserts lm_data_xfern if lm_rdyn was
48
Description
Functional Description
PCI IP Core User’s Guide