PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 63

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-22. 64-bit Master Burst Write Transaction with a 64-bit Local Interface (Continued)
32-bit PCI Master with a 64-Bit Local Bus
The following discusses read and write transactions for a PCI IP core configured with a 32-bit PCI bus and a 64-bit
local bus. Two PCI data phases are required when writing or reading 64-bit data via the Local Master Interface.
The 32-bit PCI transaction, as described in the 32-Bit PCI Master and 32-Bit Local Bus section, is similar to these
transactions; however, 32-bit data on a 64-bit data path is handled differently at the Local Master Interface. When
the 64-bit target core responds to a 32-bit transaction, the upper 32 bits of the Local data bus should be ignored or
return 0’s.
With a 64-bit back-end, the address counter needs to increment only by a QWORD (eight bytes). As a result, the
local back-end control latches the complete QWORD and routes the proper DWORD to the PCI data bus. The
lm_ldata_xfern and lm_hdata_xfern signals specify which DWORD is transferred.
CLK
10
11
12
13
9
Data 1 and 2
Data 3 and 4
Data 5 and 6
Turn around
Phase
Idle
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
With both devseln and lm_rdyn asserted in the previous cycle, the Core asserts irdyn, and it
prepares for the 64-bit write burst. So it asserts lm_ldata_xfern and lm_hdata_xfern to the
local master to signify Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0] are being read and will be transferred to the PCI bus.
The Core keeps framen asserted and asserts irdyn. It also keeps lm_ldata_xfern and
lm_hdata_xfern de-asserted to the local master to signify Data 3 and Data 4 on
l_ad_in[63:0] are not read.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
With lm_ldata_xfern and lm_hdata_xfern asserted on the previous cycle, the local master
should increment the address counter.
Since Data 1 and Data 2 on the PCI bus were read by the target, the Core transfers Data 3 and
Data 4 and their byte enables to ad[63:0] and cben[7:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted.
With lm_ldata_xfern and lm_hdata_xfern asserted on the previous cycle, the local master
provides Data 5 and Data 6 on l_ad_in[63:0] and the byte enables on lm_cben_in[7:0].
Because both lm_rdyn and trdyn were asserted on the previous cycle, the Core asserts
lm_ldata_xfern and lm_hdata_xfern to the local master to signify Data 5 and Data 6 on
l_ad_in[63:0] and the byte enables on lm_cben_in[7:0] are being read and will be trans-
ferred to the PCI bus. Because Data 5 and Data 6 are the last data, the local master de-asserts
lm_rdyn. The Core keeps framen asserted to signify the burst continues. Since both irdyn and
trdyn are asserted, the second data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
Since Data 3 and Data 4 on PCI bus were read, the Core transfers Data 5 and Data 6 and their
byte enables to ad[63:0] and cben[7:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted.
Because the current transaction is the last, the Core de-asserts framen and req64n to signal the
end of the burst, also it de-asserts lm_ldata_xfern and lm_hdata_xfern.
Since both irdyn and trdyn are asserted, the third data phase is completed on this cycle.
The Core relinquishes control of framen, req64n, ad and cben. It de-asserts irdyn, decreases
‘lm_burst_cnt’ to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle. The target de-asserts devseln, ack64n and trdyn.
The Core relinquishes control of irdyn, par and par64.
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Description
Functional Description
PCI IP Core User’s Guide