PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 50

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-18. 32-bit Master Write Transaction with Local Wait State (Continued)
CLK
10
11
12
13
5
6
7
8
9
Turn around
PCI Data
Address
Phase
Data 1
Data 2
data 3
Wait
Wait
Idle
Idle
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the starting address, the bus command and the burst length are
being latched.
The local master de-asserts lm_req32n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen to initiate the 32-bit write transaction when gntn was asserted and
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle, the local master provides Data 1 on
l_ad_in[31:0] and byte enable 1 on lm_cben_in[3:0]. And the Core asserts
lm_data_xfern to the local master to signify these data and byte enables are being read and will
be transferred to the PCI bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it keeps lm_rdyn de-
asserted until it is ready.
If the target completes the fast decode and is ready to receive 32-bit data, it asserts devseln and
trdyn.
The Core de-asserts reqn when framen was asserted and lm_req32n was de-asserted on the
previous cycle.
With lm_data_xfern asserted on the previous cycle that was the address phase, the local mas-
ter increments the address counter while the Core transfers Data 1 and the byte enables to
ad[31:0] and cben[3:0].
Because lm_rdyn was asserted on the previous cycle, the local master provides Data 2 on
l_ad_in[31:0] and byte enable 2 on lm_cben_in[3:0]. And the Core asserts
lm_data_xfern to the local master to signify these data and byte enables are being read and will
be transferred to the PCI bus. Data 2 will be buffered and put on PCI bus after Data 1 phase fin-
ished.
The local master de-asserts lm_rdyn to inform the Core it isn’t ready for Data 3.
The Core de-asserts lm_gntn to follow gntn. It asserts irdyn. Framen, Data 1 and the byte
enable 1 are kept on the PCI bus. Since the irdyn and trdyn are asserted, the first data phase is
completed. The Core de-asserts lm_data_xfern if lm_rdyn was de-asserted on the previous
cycle.
The Core asserted irdyn if it has gotten Data 2 from local master interface. It transfers Data 2
and byte enable 2 on ad[31:0] and cben[3:0] respectively.
The target keeps devseln and trdyn. Data 2 phase is completed.
Since the previous data phase was completed, the Core decreases lm_burst_cnt to two.
Lm_rdyn is asserted to ready for Data3.
Since the Core has not gotten Data 3 from local master interface. It de-asserts irdyn to inform a
wait cycle.
Because lm_rdyn was asserted on the previous cycle, the local master provides Data 3 on
l_ad_in[31:0] and byte enable 3 on lm_cben_in[3:0]. And the Core asserts
lm_data_xfern to local master to signify these data and byte enables are being read and will be
transferred to the PCI bus.
Since the previous data phase was completed, the Core decreases lm_burst_cnt to one.
The Core asserts irdyn and de-asserts framen to inform the last data phase. It transfer Data 3
and byte enable The third data phase is completed.
The Core relinquishes control of framen, ad and cben. It de-asserts irdyn, decreases
lm_burst_cnt to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle.
The Core relinquishes control of irdyn, par.
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Description
Functional Description
PCI IP Core User’s Guide