PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 128

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-46. 32-bit Target Disconnect Without Data for Read Transaction
Table 2-52. 32-bit Target Disconnect Without Data for Read Transaction
Figure 2-47
CLK
4
5
6
7
8
9
lt_disconnectn
lt_addressout
lt_data_xfern
l_ad_in[31:0]
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
lt_r_nw
framen
and
lt_rdyn
stopn
trdyn
irdyn
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal is driven low to indicate that the back-end application is ready to provide data on the next clock cycle.
The lt_data_xfern signal is driven low by the PCI IP core to indicate that data is valid on
l_ad_in[31:0].Because the target can not complete any more PCI data phases the lt_rdyn signal is driven
high and lt_disconnectn signals are driven low.
The trdyn signal is driven low because the lt_rdyn signal was driven low two clock cycle before. The
lt_data_xfern signal is de-asserted because the lt_rdyn signal was de-asserted in the previous
cycle.Data 1 is presented to the PCI bus via ad[31:0].
The trdyn signal is de-asserted since the lt_rdyn signal was driven high two clock cycles before. The stopn
signal is asserted since the lt_disconnectn signal was driven low two clock cycles before.
The PCI master de-asserts the framen to acknowledge the disconnection initiated by the target.
The PCI master disconnects by de-asserting the irdyn. The PCI IP core disconnects from the PCI bus by de-
asserting the devseln and stopn.
par
clk
Table 2-53
1
Don’t care
Command
Address
Bus
0x00
2
illustrate a Disconnect Without Data for a write transaction.
Address
Parity
Don’t care
3
4
Don’t care
Enable 1
Byte
Data Parity 1
5
Data 1
128
6
Description
Data 1
0x01
7
Address
Data Parity
1
Don’t care
Don’t care
8
Don’t care
9
Don’t care
Functional Description
10
PCI IP Core User’s Guide
11
0x00
12