PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 33

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-11. 32-bit Master Single Read Transaction with a 32-Bit Local Interface
CLK
10
1
2
3
4
5
6
7
8
9
Turn around
Turn around
Address
Phase
Data 1
Idle
Idle
Idle
Idle
Idle
Idle
The lm_req32n signal is asserted by the master application logic on the Local Master interface
for the 32-bit data transaction request. The Local Master interface drives the PCI starting
address, the bus command, and the burst transaction length during the same clock cycle on
l_ad_in, lm_cben_in and lm_burst_length, respectively.
The Core's Local Master Interface detects the asserted lm_req32n and asserts reqn to
request the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The
Core asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is
changed to ‘Address Loading’ to indicate the starting address, the bus command, and the burst
length are being latched.
The Core asserts framen to start transaction and the local master de-asserts lm_req32n
when the previous lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request
fast back-to-back PCI bus transaction.
Since lm_status[3:0] was ‘Address Loading’ on the previous cycle. The Core drives the PCI
starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it
outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[3:0]. Asserting lm_rdyn also
means the local master is ready to read data. If it is not ready to read data, it keeps lm_rdyn de-
asserted until it is ready.
The Core de-asserts reqn when framen was asserted and lm_req32n was de-asserted on the
previous cycle.
The Core tri-states the ad[31:0] lines and drives the byte enables (Byte Enable 1). Since
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read
data. Because this is a single data phase transaction, the master de-asserts framen simultane-
ously.
The target asserts devseln to claim the transaction.
The Core de-asserts lm_gntn to follow gntn.
The target asserts trdyn and puts Data 1 on ad[31:0].
If the local master is ready to read the first DWORD, lm_rdyn remains asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
The Core relinquishes control of framen and cben. It de-asserts irdyn and changes the status
of lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted during the last cycle.
Since the previous data phase was completed, the Core transfers Data 1 on
l_data_out[31:0] and decreases the lm_burst_cnt to zero.
The target relinquishes control of ad[31:0]. It de-asserts devseln and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 1 is available on l_data_out[31:0]. With
lm_data_xfern asserted, the local master safely reads Data 1.
The master relinquishes control of irdyn and de-asserts lm_data_xfern, and the local mas-
ter de-asserts lm_rdyn.
33
Description
Functional Description
PCI IP Core User’s Guide