PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 59

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-21. 64-bit Master Burst Read Transaction with a 64-bit Local Interface
CLK
1
2
3
4
5
6
7
8
9
Data 1 and 2
Data 3 and 4
Turn around
Address
Phase
Idle
Idle
Idle
Idle
Idle
The local master asserts lm_req64n to request 64-bit wide data transaction. It also issues the
PCI starting address, the bus command and the burst length will be available on l_ad_in,
lm_cben_in and lm_burst_length respectively on the same clock cycle.
The Core’s Local Master Interface detects the asserted lm_req64n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req64n and lm_gntn were asserted on the previous cycle, lm_status[3:0] is
changed to ‘Address Loading’ to indicate the starting address, the bus command and the burst
length are being latched.
The local master de-asserts lm_req64n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen and req64n to initiate the 64-bit read transaction when gntn was still
asserted and lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the
PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it
outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[7:0]. Asserting lm_rdyn also
means the local master is ready to read data. If it is not ready to read data, it keeps lm_rdyn de-
asserted until it is ready.
The Core de-asserts reqn when framen was asserted but lm_req64n was de-asserted on the
previous cycle.
The target asserts devseln and ack64n to indicate it acknowledges the 64-bit transaction. The
Core tri-states the ad[63:0] lines and drives the byte enables (Byte Enable 1 and 2). Since
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read data.
Because the Core performs burst data transfer, it keeps framen asserted.
The Core asserts lm_64bit_transn to indicate the current data transaction is 64 bits wide. It
de-asserts lm_gntn to follow gntn.
The target asserts trdyn and puts Data 1 and 2 on ad[63:0].
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
The Core keeps framen asserted to the target to signify the burst continues. It de-asserts
lm_gntn to follow gntn.
If the local master is ready to read the first QWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 1 and 2 on
l_data_out[63:0] and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_ldata_xfern and lm_hdata_xfern to the local master to signify Data 1 and 2 are avail-
able on l_data_out[63:0]. With lm_ldata_xfern and lm_hdata_xfern asserted, the
local master can safely read Data 1 and 2 and increment the address counter.
If the local master keeps lm_rdyn asserted on the previous cycle, the Core keeps irdyn
asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next QWORD
(Data 3 and 4) on ad[63:0].
If the local master is ready to read the next QWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
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Description
Functional Description
PCI IP Core User’s Guide