PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 76

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-26. 32-bit Master Dual Address Cycle – Write Transaction (Continued)
Fast Back-to-Back Transactions
The PCI IP core, as a master, is capable of executing fast back-to-back transactions if two or more consecutive
transactions are required. The fast back-to-back transaction consists of two or more complete PCI transactions
without an idle state between them. To execute fast back-to-back transaction with the PCI IP core, lm_req32n or
lm_req64n must be asserted once lm_status changes to the ‘Address Loading’ state. Otherwise, the assertion
will not be recognized and the next transaction will be treated as a basic transaction having the ‘Idle State’ on the
PCI bus. An effective way for handling fast back-to-back transfers is to keep lm_req32n or lm_req64n asserted
until required data has been transferred.
For fast back-to-back transaction, the previous transaction must be a write transaction.
Figure 2-23
interface correlates to the Local Master Interface. The table explains each event in the figure with a clock-by-clock
description.
CLK
11
12
13
and
Turn around
Phase
Data 3
Table 2-27
Idle
Since the previous data phase was completed, the Core decreases lm_burst_cnt.
Since Data 2 on the PCI bus were read, the Core transfers Data 3 and their byte enables to
ad[31:0] and cben[3:0].
Because the current transaction is the last, the Core de-asserts framen to signal the end of the
burst and it de-asserts lm_data_xfern.
Since both irdyn and trdyn are asserted, the third data phase is completed on this cycle.
The Core relinquishes control of framen, ad and cben. It de-asserts irdyn, decreases
lm_burst_cnt to zero and changes lm_status[3:0] into ‘Bus Termination” with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted dur-
ing the last cycle. The target de-asserts devseln and trdyn.
The Core relinquishes control of irdyn and par.
illustrate a 64-bit, fast back-to-back write transaction. The figure illustrates how the PCI
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Description
Functional Description
PCI IP Core User’s Guide