PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 56

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-20. 32-bit Master Burst Write Transaction with a 32-Bit Local Interface (Continued)
CLK
10
11
12
6
7
8
9
Turn around
Address
Phase
Data 1
Data 2
Data 3
Wait
Idle
The local master de-asserts lm_req32n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen to initiate the 32-bit write transaction when gntn was asserted and
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master should provide Data 1 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0]. And the Core asserts lm_data_xfern to the local master to signify these
data and byte enables are being read and will be transferred to the PCI bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it should keep
lm_rdyn de-asserted until it is ready.
The Core de-asserts reqn after the assertion of framen.
lm_data_xfern is asserted to signify Data 2 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0] are being read and will be transferred to the PCI bus.
If the local master is ready to provide the next DWORD, it keeps lm_rdyn asserted.
The Core keeps framen asserted and asserts irdyn. It also de-asserts lm_data_xfern to the
local master to signify Data 3 on l_ad_in[31:0] is not read.
If the local master is ready to provide the next DWORD, it keeps lm_rdyn asserted.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases lm_burst_cnt.
Since Data 1 on PCI bus were read by the target, the Core transfers Data 2 and their byte enables
to ad[31:0] and cben[3:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted.
Because both lm_rdyn and trdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 3 on l_ad_in[31:0] and the byte enables
on lm_cben_in[3:0] are being read and will be transferred to the PCI bus.
Because Data 3 are the last data, the local master de-asserts lm_rdyn.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases lm_burst_cnt.
Since Data 2 on the PCI bus were read, the Core transfers Data 3 and their byte enables to
ad[31:0] and cben[3:0].
Because the current transaction is the last, the Core de-asserts framen to signal the end of the
burst, also it de-asserts lm_data_xfern.
Since both irdyn and trdyn are asserted, the third data phase is completed on this cycle.
The Core relinquishes control of framen, ad and cben. It de-asserts irdyn, decreases
lm_burst_cnt to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle. The target de-asserts devseln and trdyn.
The Core relinquishes control of irdyn and par.
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Description
Functional Description
PCI IP Core User’s Guide