PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 67

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-23. 32-bit Master Burst Read Transaction with a 64-Bit Local Interface (Continued)
CLK
10
11
12
12
Turn around
Phase
Data 3
Data 4
Idle
Since the previous data phase was completed, the Core transfers Data 2 on
l_data_out[63:32] and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core de-asserts
lm_ldata_xfern and asserts lm_hdata_xfern to the local master to signify Data 2 are avail-
able on l_data_out[63:32]. With lm_hdata_xfern asserted, the local master can safely
read Data 2 and increment the address counter.
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted. If the target is still
ready to provide data, it keeps trdyn asserted and drives the next DWORD (Data 3) on
ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the third data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 3 on l_data_out[31:0]
and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_ldata_xfern and de-asserts lm_hdata_xfern to the local master to signify Data 3 are
available on l_data_out[31:0]. With lm_ldata_xfern asserted, the local master can safely
read Data 3 and increment the address counter.
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
Because the current transaction is the last, the Core de-asserts framen and req64n to signal the
end of the burst. If the target is still ready to provide data, it keeps trdyn asserted and drives the
next DWORD (Data 4) on ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the fourth data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 4 on
l_data_out[63:32] and decreases the lm_burst_cnt to zero.
The Core relinquishes control of framen, req64n and cben. It de-asserts irdyn and changes
lm_status[3:0] into ‘Bus Termination’ with lm_termination as ‘Normal Termination’
because both trdyn and irdyn were asserted last cycle.
The target relinquishes control of ad[31:0]. It de-asserts devseln and trdyn.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core de-asserts
lm_ldata_xfern and asserts lm_hdata_xfern to the local master to signify Data 4 are avail-
able on l_data_out[63:32]. With lm_hdata_xfern asserted, the local master can safely
read Data 4.
The Core relinquishes control of irdyn and de-asserts lm_ldata_xfern and
lm_hdata_xfern, and the local master de-asserts lm_rdyn since all of the burst data have
been read.
67
Description
Functional Description
PCI IP Core User’s Guide