PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 146

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
IPexpress-Created Files and Top Level Directory Structure
When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are
generated in the specified “Project Path” directory. The directory structure of the generated files is shown in
Figure
device.
Figure 4-3. PCI IP Core Directory Structure
Table 4-1
press tool creates several files that are used throughout the design cycle. The names of most of the created files
are customized to the user’s module name specified in the IPexpress tool.
Table 4-1. File List
Table 4-2
generation capability are generated in the user's project directory.
Table 4-2. Additional Files
<username>.lpc
<username>.ipx
<username>.ngo
<username>_bb.v/.vhd
<username>_inst.v/.vhd
<username>_beh.v/.vhd
<username>_generate.tcl
<username>_generate.log
4-3. This example shows the directory structure generated with the PCI Master/Target 33 for LatticeECP3
provides a list of key files and directories created by the IPexpress tool and how they are used. The IPex-
provides a list of key additional files providing IP core generation status information and command line
File
File
This file contains the IPexpress tool options used to recreate or modify the core in the IPexpress
tool.
The IPX file holds references to all of the elements of an IP or Module after it is generated from
the IPexpress tool (Diamond version only). The file is used to bring in the appropriate files during
the design implementation and analysis. It is also used to re-load parameter settings into the
IP/Module generation GUI when an IP/Module is being re-generated.
This file provides the synthesized IP core.
This file provides the synthesis black box for the user’s synthesis.
This file provides an instance template for the PCI IP core.
This file provides the front-end simulation library for the PCI IP core.
This file is created when the GUI “Generate” button is pushed. This file may be run from com-
mand line.
This is the synthesis and map log file.
146
Description
Description
PCI IP Core User’s Guide
IP Core Generation