PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 2

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Chapter 1. Introduction .......................................................................................................................... 6
Chapter 2. Functional Description ...................................................................................................... 11
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG18_09.2, November 2010
Quick Facts ........................................................................................................................................................... 6
Features .............................................................................................................................................................. 10
Block Diagram..................................................................................................................................................... 11
Signal Descriptions ............................................................................................................................................. 13
PCI Configuration Space Setup .......................................................................................................................... 18
Lattice PCI IP core Configuration Options .......................................................................................................... 24
Local Bus Interface ............................................................................................................................................. 30
Basic PCI Master Read and Write Transactions................................................................................................. 31
Advanced Master Transactions........................................................................................................................... 46
Master and Target Termination........................................................................................................................... 81
Basic PCI Target Read and Write Transactions ................................................................................................. 81
PCI Master Control..................................................................................................................................... 11
PCI Target Control ..................................................................................................................................... 12
Local Master Interface Control ................................................................................................................... 12
Local Target Control................................................................................................................................... 13
Configuration Space................................................................................................................................... 13
Parity Generator and Checker ................................................................................................................... 13
PCI Interface Signals ................................................................................................................................. 14
Local Interface Signals............................................................................................................................... 15
Status Register........................................................................................................................................... 21
Base Address Registers............................................................................................................................. 22
BAR Mapped to Memory Space................................................................................................................. 22
Bar Mapped to I/O Space........................................................................................................................... 23
Cache Line Size ......................................................................................................................................... 23
Latency Timer ............................................................................................................................................ 23
CardBus CIS Pointer.................................................................................................................................. 23
Subsystem Vendor ID ................................................................................................................................ 23
Subsystem ID............................................................................................................................................. 23
Capabilities Pointer .................................................................................................................................... 24
Min_Gnt...................................................................................................................................................... 24
Max_Lat ..................................................................................................................................................... 24
Interrupt Line .............................................................................................................................................. 24
Interrupt Pin................................................................................................................................................ 24
Reserved.................................................................................................................................................... 24
IPexpress User-Controlled Configurations................................................................................................. 24
PCI Configuration Using Core Configuration Space Port........................................................................... 25
Target Operation ........................................................................................................................................ 30
Master Operation ....................................................................................................................................... 30
32-bit PCI Master with a 32-bit Local Bus .................................................................................................. 31
64-Bit PCI Master with a 64-Bit Local Bus ................................................................................................. 35
32-bit PCI Master with a 64-Bit Local Bus.................................................................................................. 40
Configuration Read and Write Transactions .............................................................................................. 46
PCI Master I/O Read and Write Transactions............................................................................................ 46
Wait States................................................................................................................................................. 46
Burst Read and Write Master Transactions ............................................................................................... 51
Dual Address Cycle (DAC)......................................................................................................................... 70
Fast Back-to-Back Transactions ................................................................................................................ 76
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Table of Contents
PCI IP Core User’s Guide