PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 134

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-56. 32-bit Target Abort for Read Transaction
Figure 2-51
Figure 2-51. 32-bit Target Abort for Write Transaction
CLK
4
5
6
7
8
9
l_data_out[31:0]
lt_addressout
lt_data_xfern
bar_hit[5:0]
cben[3:0]
and
lt_abortn
ad[31:0]
devseln
signal is driven low to indicate that the back-end application is ready to put data out on the next cycle.
The lt_data_xfern signal is driven low by the PCI IP core to the back-end to indicate that data on l_ad_in is
being read.The lt_rdyn signal is driven low to indicate the back-end is ready to provide the next data.
The trdyn signal is driven low because the lt_rdyn signal was driven low two clock cycles before. The
lt_data_xfern signal is asserted because the lt_rdyn signal was asserted in the previous cycle.
Data 1 is presented to the PCI bus via ad[31:0].
Because the back-end wants to abort the transaction the lt_abortn signal is driven low. The data on l_ad_in is
also invalid.
A target abort is requested as the devseln and the trdyn signals are de-asserted and the stopn signal is
asserted.
The PCI master de-asserts the framen to acknowledge the target abort.
The PCI master terminates the transaction by de-asserting the irdyn. The PCI IP core de-asserts the stopn.
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
framen
lt_r_nw
lt_rdyn
stopn
trdyn
irdyn
par
clk
Table 2-57
1
Don’t care
Command
Address
Bus
0x00
2
show a target abort on a write transaction.
Address
Parity
3
Don’t care
Byte Enable 1
4
Data 1
Data Parity 1
5
134
6
Description
Enable 2
Data 2
Data 1
0x01
Byte
7
Address
Data Parity
2
Don’t care
Don’t care
8
Don’t care
9
Don’t care
Don’t care
Functional Description
10
PCI IP Core User’s Guide
11
0x00
12