PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 81

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Master and Target Termination
The signal lm_termination[2:0] indicates the different types of Master-initiated terminations. In addition, the
state of the target’s response when the master executes the transaction is made available for the user’s master
application. This enables the master application to complete, terminate or refer the transaction to software via inter-
rupt.
The master-initiated early termination commands include timeout and Master Abort. When the master’s gntn line
is de-asserted and its internal latency timer is expired, the master ends the current transaction. When it doesn’t
detect the assertion of devseln within the required period after it asserts framen, the master terminates the cur-
rent transaction. This is called Master Abort termination.
The back-end application monitors and controls early termination of PCI transactions by asserting lm_abortn.
Any lm_abortn assertion is ignored during ‘Address Loading’ and the first clock cycle of ‘Bus Transaction’. If
lm_abortn is asserted after first clock cycle of ‘Bus Transaction’, the transaction is terminated at next data phase.
When next clock cycle is a wait cycle, the transaction is not terminated until one data phase is completed, except
when the target aborts the transaction.
A summary of the four types of target-initiated termination commands are described in
Table 2-28. Master Initiated Termination Summary
Basic PCI Target Read and Write Transactions
Read and write transactions to memory and I/O space are used to transfer data on the PCI bus. The basic read
and write transactions use the following PCI commands:
• I/O Read
• I/O Write
• Memory Read
• Memory Write
• Configuration Read
• Configuration Write
To make the integration of the PCI IP core as simple as possible, the basic transactions are described based on dif-
ferent bus configurations supported with this PCI IP core. Although the fundamentals of the basic transactions are
the same, different bus configurations require slightly different local bus signaling. The PCI and local bus configura-
tions do not affect configuration access because configuration accesses require no local bus intervention. Refer to
the following sections for more information on the basic bus transactions with specific PCI IP core configurations:
Lm_termination[2:0]
000
001
010
011
100
101
110
111
Normal termination
Timeout termination
No target response termination
Target abort termination
Retry termination
Disconnect data termination
Grant abort termination
Local master termination
Name
Normal Termination takes place.
The cycle timed out.
Also known as Master Abort. The Master terminates the transaction
because devseln was not asserted during the expected time.
The Target issues an abort termination
The target of the transaction is not ready for the transaction. The
Master issues a retry.
The target device is terminating the burst transaction.
A Grant termination has occurred.
The Local Interface cannot complete the transaction.
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Description
Functional Description
Table
PCI IP Core User’s Guide
2-28.