PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 127

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-51. 32-bit Target Disconnect with Data for Write Transaction
Disconnect Without Data
A Disconnect Without Data occurs after at least one data DWORD or QWORD has been transferred. A Disconnect
Without Data is used if the PCI IP core is incapable of completing the current PCI data phase.
Table 2-52
Below is a list of the reasons that the PCI IP core may Disconnect Without Data:
• Target slow to complete subsequent data phase
• Target does not support burst mode requested
• Memory target doesn’t understand addressing sequence
• Transfer crosses over target’s address boundary
CLK
4
5
6
7
8
show a Disconnect Without Data for a read transaction.
The devseln signal is driven low to indicate that the PCI IP core has been selected for the transaction. The
lt_rdyn signal is driven low to indicate that the back-end application is ready to receive data. Because the tar-
get can not complete any more PCI data phases the lt_disconnectn signal is also driven low.
The trdyn and the stopn signals are driven low because both the lt_rdyn and the lt_disconnectn signals
were driven low the previous cycle.
The target asserts lt_data_xfern to the back-end to signify Data 1 is available on the lt_data_out.
The PCI IP core de-asserts trdyn since the last PCI data phase was complete and the stopn was asserted.
The PCI master de-asserts the framen to acknowledge the disconnection initiated by the target.
The PCI master disconnects by de-asserting irdyn. The PCI IP core disconnects from the PCI bus by de-
asserting devseln and stopn.
The target relinquishes devseln, stopn and trdyn.
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Description
Functional Description
PCI IP Core User’s Guide
Figure 2-46
and