PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 79

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-27. Fast Back-to-Back Transaction (Continued)
CLK
10
11
12
9
Data 1 and 2
Data 3 and 4
PCI Data
Address
Phase
Wait
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
With both devseln and lm_rdyn asserted previous cycle, the Core asserts irdyn, and it pre-
pares for the 64-bit write burst. So it asserts lm_ldata_xfern and lm_hdata_xfern to the
local master to signify Data 3 and Data 4 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0] are being read and will be transferred to the PCI bus.
The Core keeps framen asserted and irdyn de-asserted. It also keeps lm_ldata_xfern and
lm_hdata_xfern de-asserted to the local master to signify Data 3 and Data 4 on
l_ad_in[63:0] are not read.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted. Because the
Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
At the last data phase of first transaction, the Core inserts a wait cycle to prepare next transaction.
So it de-asserts irdyn and changes lm_status[3:0] from ‘Bus Transaction’ to ‘Fast
Back2Back’, and it also de-asserts lm_ldata_xfern and lm_data_xfern.
With lm_ldata_xfern and lm_hdata_xfern asserted on the previous cycle, the local master
should put next transaction’s address, bus command and burst length on l_ad_in[31:0],
lm_cbe_in[3:0] and lm_burst_length[11:0] respectively.
Since Data 1 and Data 2 on PCI bus were read by the target, the Core transfers Data 3 and Data 4
and their byte enables to ad[63:0] and cben[7:0].
The Core de-asserts framen and req64n, asserts irdyn to signal Data 3 and 4 transferred.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
If both lm_req64n and lm_gntn were asserted on the previous cycle, lm_status[3:0] is
changed to ‘Address Loading’ to indicate the starting address, the bus command and the burst
length are being latched.
The local master de-asserts lm_req64n when the previous lm_status[3:0] was ‘Address
Loading’.
The Core asserts framen and req64n to initiate the second 64-bit write transaction when gntn
was asserted and lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives
the PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same
cycle, it outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the
address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides Data 5 and Data 6 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0]. And the Core asserts lm_ldata_xfern and lm_hdata_xfern to the local
master to signify these data and byte enables are being read and will be transferred to the PCI
bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it keeps lm_rdyn de-
asserted until it is ready.
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Description
Functional Description
PCI IP Core User’s Guide