PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 147

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 4-2. Additional Files (Continued)
Instantiating the Core
The
(<userame>_inst.v/vhd) templates (Verilog or VHDL) that can be used to instantiate the core in a top-level design.
An example RTL top-level reference source file that can be used as an instantiation template for the IP core is pro-
vided in <project_dir>\pci_master_target_eval\<username>\src\rtl\top. Users may also use this
top-level reference as the starting template for the top-level for their complete design.
Running Functional Simulation
Simulation support for the PCI IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator and Mentor
Graphics ModelSim (Verilog only) simulator.
The functional simulation includes a PCI bus stimulus module (pci_stim_tb) and a local module (lt_stim_tb), which
is instantiated in a top level (pci_testbench_top). Module pci_stim_tb simulates a master PCI to configure PCI core
and test the core's basic read/write command.
The generated IP core package includes behavior model (<username>_beh.v) for functional simulation in the “Proj-
ect Path” root directory, which <username>_beh.v is instantiated in PCI top model
(\<project_dir>\pci_master_target_eval\<username>\src\rtl\top).
The simulation script supporting ModelSim evaluation simulation is provided in
\<project_dir>\pci_master_target_eval\<username>\sim\modelsim.
The simulation script supporting Aldec evaluation simulation is provided in
\<project_dir>\pci_master_target_eval\<username>\sim\aldec.
The Test Application Design is instantiated in a test-bench provided in
\<project_dir>\pci_master_target_eval\testbench.
Both ModelSim and Aldec simulation is supported via test bench files provided in
\<project_dir>\pci_master_target_eval\testbench. Models required for simulation are provided in
the corresponding \models folder.
Users may run the Aldec evaluation simulation by doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro.
3. Browse to folder \<project_dir>\pci_master_target_eval\<username>\sim\aldec and execute
Users may run the ModelSim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder
3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation completes, displayed on the console are:
<< Simulation complete... >>
<username>_gen.log
one of the “do” scripts shown.
<project_dir>\pci_master_target_eval\<username>\sim\modelsim.
generated
PCI
IP
This is the IPexpress IP generation log file
core
package
includes
147
black-box
(<username>_bb.v/vhd)
PCI IP Core User’s Guide
IP Core Generation
and
instance