PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 101

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
32-Bit PCI Bus and a 32-Bit Local Bus
The following section discusses read and write, burst transactions for a PCI IP core configured with a 32-bit PCI
bus and a 32-bit Local bus.
how the PCI interface correlates to the Local Target Interface. The table gives a clock-by-clock description of each
event that occurs in the figure.
Figure 2-34. 32-bit Target Burst Read Transaction with a 32-bit Local Interface
Table 2-39. 32-bit Target Burst Read Transaction with a 32-bit Local Interface
CLK
1
2
3
lt_command_out[3:0]
lt_cben_out[3:0]
lt_address_out
lt_data_xfern
l_ad_in[31:0]
Turn around
bar_hit[5:0]
lt_access
PCI Data
cben[3:0]
Address
ad[31:0]
devseln
lt_r_nw
Phase
framen
lt_rdyn
Wait
trdyn
irdyn
par
clk
1
Don’t care
Don’t care
The PCI master asserts framen and drives ad[31:0] and cben[3:0].
The PCI master tri-states ad[31:0] and drives the first byte enables (Byte Enable 1) on
cben[3:0]. If the PCI master is ready to receive data, it asserts irdyn.The Core starts to
decode the address and command and drives the lt_address_out to the back-end application.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use the bar_hit as a chip select.
Command
Address
Bus
Figure 2-34
Don’t care
0x00
2
Address
Parity
Don’t care
3
and
Table 2-39
4
Don’t care
5
101
show a 32-bit burst read transaction. The figure illustrates
Byte Enable 1
Don’t care
Data 1
6
Description
Bus Command
Byte Enable 1
Address
Data 1
Data 2
0x01
7
Data Parity
Data 2
Data 3
1
8
Data Parity
Data 3
2
Functional Description
9
PCI IP Core User’s Guide
Data Parity
Don’t care
3
10
Don’t care
0x00
11