PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 118

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-41. 32-bit Target Fast Back-to-Back Transaction
Table 2-46. 32-bit Target Fast Back-to-Back Transaction
CLK
1
2
3
4
5
6
7
8
l_data_out[31:0]
lt_addressout
lt_data_xfern
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
lt_r_nw
framen
lt_rdyn
Address
Wait
Wait
Wait
Data 1
Address
Wait
Wait
irdyn
trdyn
par
clk
PCI Data
Phase
1
Don’t care
Command
Address
Bus
0x00
The PCI master asserts framen and drives ad[31:0] and cben[3:0].
The PCI master drives the first byte enables (Byte Enable 1) on cben[3:0]. If the master is ready
to write data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].
The Core starts to decode the address and command. The target drives the lt_address_out to
the back-end application.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
application can use bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after bar_hit. If
the back-end will be ready in two cycles to write data, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
The master asserts framen and drives the ad[31:0] and cben[3:0].
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core asserts
lt_data_xfern to the back-end to signify Data 1 is valid. With lt_data_xfern asserted the
back-end can safely write Data 1.
The PCI master drives the first byte enables (Byte Enable 1) on cben[3:0]. If the master is ready
to write data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].
The Core starts to decode the address and command. The Core drives the lt_address_out to
the back-end.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use bar_hit as a chip select.
2
Address
Parity
3
Don’t care
Byte Enable 1
4
Data 1
Address
Data Parity 1
5
0x01
6
118
Command
Address
Data 1
Bus
7
Address
Description
Parity
0x00
8
Byte Enable 2
Don’t care
9
Data 2
Data Parity 2
10
Address
0x01
Functional Description
PCI IP Core User’s Guide
11
Data 2
12
Don’t care
0x00
13