PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 61

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-18
lates to the Local Master Interface. The table gives a clock-by-clock description of each event that occurs in the fig-
ure.
Figure 2-18. 64-bit Master Burst Write Transaction with a 64-bit Local Interface
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_64bit_transn
lm_cben_in[3:0]
lm_cben_in[7:4]
lm_hdata_xfern
and
lm_ldata_xfern
l_ad_in[63:32]
lm_status[3:0]
l_ad_in[31:0]
lm_req64n
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
lm_gntn
lm_rdyn
devseln
framen
ack64n
req64n
par64
irdyn
trdyn
reqn
gntn
Table 2-22
par
clk
1
2
illustrate a 64-bit burst write transaction. The figure shows how the PCI interface corre-
Termination
Bus
3
Bus Length
Don’t care
Command
Don’t care
Don’t care
Address
( = 3 )
Bus
4
5
Don’t care
Don’t care
Address
Loading
Don’t care
Don’t care
6
Don’t care
Don’t care
Command
Address
Enable 1
Enable 2
Data 1
Data 2
Byte
Byte
61
Bus
Don’t care
7
Address
Parity
Bus Length
8
( = 3 )
Byte Enable 1
Byte Enable 2
Byte Enable 3
Byte Enable 4
Data 1
Data 2
Data 3
Data 4
Transaction
9
Bus
Data Parity 1
Data Parity 2
Don’t care
10
Enable 3
Enable 4
Enable 5
Enable 6
Data 3
Data 4
Data 5
Data 6
Byte
Byte
Byte
Byte
2
11
Functional Description
Enable 5
Enable 6
Parity 3
Parity 4
Data 5
Data 6
Data
Data
Byte
Byte
1
PCI IP Core User’s Guide
12
Don’t care
Don’t care
Don’t care
Don’t care
Parity 5
Parity 6
Data
Data
Termination
Termination
13
Normal
Bus
0
14