PCI-T32-XP-N2 Lattice, PCI-T32-XP-N2 Datasheet - Page 158

• Manufacturer Part Number: PCI-T32-XP-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 32B
• Manufacturer: Lattice

Specifications of PCI-T32-XP-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
LatticeXP2 FPGAs
Table A-11. Performance and Resource Utilization
Ordering Part Number
Table A-12
LatticeXP2.
Table A-12. OPN for LatticeXP2 PCI IP Core
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Target 33 MHz, 64-bit PCI/
Local/Address bus width
Target 66 MHz, 32-bit PCI/
Local/Address bus width
Target 66 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 64-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LFXP2-17E-6F484C device with Lattice Diamond 1.0 software. Performance may
vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.
User-Configurable Mode
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for
IPexpress
33 MHz
33 MHz
66 MHz
66 MHz
33 MHz
33 MHz
66 MHz
66 MHz
Speed
PCI Bus
SLICEs
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
1100
1081
1530
588
707
601
827
851
LUTs
1342
1060
1553
1692
2572
Master/Target
Master/Target
Master/Target
Master/Target
709
919
964
1
158
Target
Target
Target
Target
Type
Registers
470
592
491
612
640
847
661
867
PCI-MT32-X2-U6
PCI-MT64-X2-U6
PCI-MT32-X2-U6
PCI-MT64-X2-U6
PCI-T32-X2-U6
PCI-T64-X2-U6
PCI-T32-X2-U6
PCI-T64-X2-U6
sysMEM
EBRs
OPN
0
0
0
0
0
0
0
0
(PCI Interface)
External Pins
Resource Utilization
PCI IP Core User’s Guide
48
87
48
87
50
89
50
89
f
MAX
33
33
66
66
33
33
66
66