MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 132
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Cache Organization
4.8 Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 128 sets in
the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte
instruction cache has 256 sets. Entire cache lines are loaded from memory by burst-mode
accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for
the cache line to be valid.
Figure 4-3 shows data cache organization as well as terminology used.
A set is a group of four lines (one from each level, or way), corresponding to the same index
into the cache array.
4.8.1 Cache Line States: Invalid, Valid-Unmodified, and
As shown in Table 4-3, a data cache line can be invalid, valid-unmodified (often called
exclusive), or valid-modified. An instruction cache line can be valid or invalid.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
4-8
Set 0
Set 1
Set 126
Set 127
V
0
1
1
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line (data cache only)
Valid-Modified
M
0
1
x
TAG
Invalid. Invalid lines are ignored during lookups.
Valid, unmodified. Cache line has valid data that matches system memory.
Valid, modified. Cache line contains most recent data, data at system memory location is stale.
Figure 4-3. Data Cache Organization and Line Format
Way 0
•
•
•
Table 4-3. Valid and Modified Bit Settings
V M
Longword 0
MCF5407 User’s Manual
Way 1
Line
•
•
•
Cache Line Format
Longword 1
Description
Way 2
•
•
•
Longword 2
Longword 3
Way 3
•
•
•
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