MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 541

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Signal descriptions, 17-1
DMR initialization, 11-37
example, 11-34
initialization code, 11-39
interface configuration, 11-34
mode register initialization, 11-38
overview, 11-1
address bus, 17-7
address configuration, 17-15
address strobe, 17-9
bus
chip-select module, 17-15
clock and reset, 17-13
clock input, 17-13
data bus, 17-8
data/configuration pins, 17-14
debug
debug module/JTAG
divide control, 17-15
DMA controller module
DRAM controller
I
interrupt control signals, 17-12
2
C module
arbitration, 17-12
clock output, 17-13
data, 17-8
driven, 17-13
grant, 17-12
request, 17-12
high impedance, 17-20
JTAG, 17-21
processor clock output, 17-20
processor status debug data, 17-21
test
test data input/development serial input, 17-22
test data output/development serial output, 17-22
test mode select/breakpoint, 17-21
test reset/development serial clock, 17-21
general, 17-17
transfer modifier/acknowledge, 17-18
address strobes, 17-16
overview, 17-16
synchronous
synchronous edge select, 17-17
write, 17-16
general, 17-20
serial clock, 17-20
serial data, 17-20
clock, 17-22
mode, 17-20
overview, 17-20
clock enable, 17-17
column address strobe, 17-17
edge select, 17-17
row address strobe, 17-17
INDEX
Index
Signals
SIM
Software watchdog
Stack pointer, 2-9, 2-9
Status register, 2-11
Supervisor
System protection control register, 6-8
T
Timer module
Timing
JTAG, 19-2
parallel I/O port, 17-19
read/write, 17-8
reset in, out, 17-13
serial module
size, 17-8
timer module, 17-19
transfer
overview, 17-1
features, 6-1
programming model, 6-3
register memory map, 6-3
interrupt vector register, 6-9
service register, 6-9
timer, 6-6
programming model, 2-10
registers, 1-16
calculating time-out values, 13-7
capture registers, 13-4
code example, 13-6
counters, 13-5
event registers, 13-5
general-purpose programming model, 13-2
general-purpose units, 13-2
mode registers, 13-3
reference registers, 13-4
branch instruction execution, 2-30
MAC unit instructions, 3-5
MOVE instructions, 2-25
one operand, 2-26
PLL, 7-4
RSTI, 7-5
two operands, 2-27
interrupt request, 17-12
clear to Send, 17-19
general, 17-18
receiver serial data input, 17-19
request to send, 17-19
transmitter serial data output, 17-18
acknowledge, 17-9
in progress, 17-10
modifier, 17-10
start, 17-9
Index-5