MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 98
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Exception Processing Overview
defined by Motorola; the remaining 192 are user-defined interrupt vectors.
ColdFire processors inhibit sampling for interrupts during the first instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary,
by raising the interrupt mask level contained in the status register.
2.8.1 Exception Stack Frame Definition
The exception stack frame is shown in Figure 2-1. The first longword of the exception stack
frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The
second longword contains the 32-bit program counter address.
2-32
1
Vector Numbers
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC
of the instruction that immediately follows the instruction that caused the fault.
64–255
16–23
25–31
32–47
48–60
62–63
6–7
10
11
12
13
14
15
24
61
0
1
2
3
4
5
8
9
Vector Offset (Hex)
080–0BC
0F8–0FC
Table 2-19. Exception Vector Assignments
018–01C
040–05C
064–07C
0C0–0F0
100–3FC
00C
02C
03C
000
004
008
010
014
020
024
028
030
034
038
060
0F4
MCF5407 User’s Manual
Stacked Program Counter
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Next
Next
Next
Next
Next
Next
Next
Next
—
—
—
—
—
—
1
Initial stack pointer
Initial program counter
Access error
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-a opcode
Unimplemented line-f opcode
Non-PC breakpoint debug interrupt
PC breakpoint debug interrupt
Format error
Uninitialized interrupt
Reserved
Spurious interrupt
Level 1–7 autovectored interrupts
Trap #0–15 instructions
Reserved
Unsupported instruction
Reserved
User-defined interrupts
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