MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 24

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
Number
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
11-18
11-19
11-20
11-21
11-22
11-23
11-24
11-25
11-26
11-27
11-28
11-29
12-1
12-2
12-3
12-4
12-6
12-5
12-7
12-8
12-9
12-10
12-11
12-12
12-13
13-1
13-2
13-3
13-4
13-5
13-6
14-1
14-2
14-3
14-4
xxiv
Write Hit in Continuous Page Mode......................................................................... 11-15
EDO Read Operation (3-2-2-2) ................................................................................ 11-15
DRAM Access Delayed by Refresh ......................................................................... 11-16
MCF5407 SDRAM Interface.................................................................................... 11-18
Using EDGESEL to Change Signal Timing............................................................. 11-19
DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19
DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20
DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22
Burst Read SDRAM Access ..................................................................................... 11-28
Burst Write SDRAM Access .................................................................................... 11-29
Synchronous, Continuous Page-Mode Access—Consecutive Reads....................... 11-30
Synchronous, Continuous Page-Mode Access—Read after Write........................... 11-31
Auto-Refresh Operation............................................................................................ 11-32
Self-Refresh Operation ............................................................................................. 11-32
Mode Register Set (mrs) Command ......................................................................... 11-34
Initialization Values for DCR ................................................................................... 11-35
SDRAM Configuration............................................................................................. 11-36
DACR Register Configuration.................................................................................. 11-36
DMR0 Register ......................................................................................................... 11-37
Mode Register Mapping to MCF5407 A[31:0] ........................................................ 11-38
DMA Signal Diagram ................................................................................................. 12-1
MCF5307/MCF5407 TM[2:0] Pin Remapping .......................................................... 12-4
Dual-Address Transfer................................................................................................ 12-4
Single-Address Transfers............................................................................................ 12-5
Destination Address Registers (DARn) ...................................................................... 12-7
Source Address Registers (SARn) .............................................................................. 12-7
Byte Count Registers (BCRn)..................................................................................... 12-8
DMA Interrupt Vector Registers (DIVRn) ............................................................... 12-11
DREQ Timing Constraints, Dual-Address DMA Transfer....................................... 12-15
Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer ................... 12-16
Single-Address DMA Transfer ................................................................................. 12-17
Timer Block Diagram ................................................................................................. 13-1
Timer Mode Registers (TMR0/TMR1) ...................................................................... 13-3
Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4
Timer Capture Register (TCR0/TCR1) ...................................................................... 13-5
Timer Counters (TCN0/TCN1)................................................................................... 13-5
Timer Event Registers (TER0/TER1)......................................................................... 13-5
Simplified Block Diagram .......................................................................................... 14-1
UART Mode Registers 1 (UMR1n)............................................................................ 14-6
UART Mode Register 2 (UMR2n) ............................................................................. 14-7
Rx FIFO Threshold Register (RXLVL)...................................................................... 14-8
DMA Control Registers (DCRn) ............................................................................... 12-8
DMA Status Registers (DSRn) ................................................................................ 12-10
ILLUSTRATIONS
MCF5407 User’s Manual
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