MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 363

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
Field
Addr
R/W
14.3.19 UART Output Port Data Registers (UOP1n/UOP0n)
In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated
by writing a 1 to UOP0n[RTS]. UOP registers have no effect in modem mode. See
Figure 14-23.
Table 14-17 describes UOP1 fields.
14.4 UART Module Signal Definitions
Figure 14-24 shows both the external and internal signal groups.
Figure 14-24. UART Block Diagram Showing External and Internal Interface Signals
7–1
0
Bits
To Interrupt
Controller
Interface
—
RTS
to CPU
Name
External Clock (TIN)
(SIM)
7
Figure 14-23. UART Output Port Data 1 Register (UOP1/UOP0)
CLKIN
Reserved, should be cleared.
Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output.
0 Not affected.
1 Asserts RTS (UOP1). Negates RTS (UOP0).
UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0)
or
Address Bus
Control
Table 14-17. UOP1/UOP0 Field Descriptions
Data
IRQ
Internal
Control
Chapter 14. UART Modules
Logic
—
UART Module
Internal Bus
0000_0000
Write only
Description
Four-Character
Transmit Buffer
Receive Buffer
Two-Character
Clock Source
Output Port
Generator
Input Port
UART Module Signal Definitions
CTS
RTS
RxD
TxD
1
External
Interface
Signals
RTS
14-21
0