MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 357

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.11 UART Receiver Buffers (URBn)
The receiver buffer for UART0 contains one serial shift register and three receiver holding
registers, which act as a FIFO. RxD is connected to the serial shift register. The CPU reads
from the top of the stack while the receiver shifts and updates from the bottom when the
shift register is full (see Figure 14-29). RB contains the character in the receiver.
3–2
Bits
1–0
Value
00
01
10
11
00
01
10
11
NO ACTION TAKEN
TRANSMITTER
ENABLE
TRANSMITTER
DISABLE
NO ACTION TAKEN
RECEIVER ENABLE
RECEIVER DISABLE
Command
Table 14-11. UCRn Field Descriptions (Continued)
—
—
Causes the transmitter to stay in its current mode: if the transmitter is enabled, it
remains enabled; if the transmitter is disabled, it remains disabled.
Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If
the transmitter is already enabled, this command has no effect.
For UART1 in modem mode, Tx FIFO can be loaded while the transmitter is
disabled, unlike in UART mode. Therefore, this command does not affect the
behavior of TxRDY. It does not automatically set TxRDY and TxEMP; however, if
no data is written to the Tx FIFO, TxEMP is set at the first frame sync after the
transmitter is enabled.
In AC ‘97 mode, TxEMP is set if Tx FIFO is empty, the transmitter is enabled, the
receiver detects a coded ready condition, and a frame sync occurs before
samples are written to the Tx FIFO.
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character
is being sent when the transmitter is disabled, transmission completes before the
transmitter becomes inactive. If the transmitter is already disabled, the command
has no effect.
In modem mode, the transmitter does not clear USRn[TxRDY] unless UART1 is
in remote loop-back or auto-echo mode. This is because in modem mode, unlike
in UART mode, the Tx FIFO may be loaded while the Tx is disabled.
Reserved, do not use.
Causes the receiver to stay in its current mode. If the receiver is enabled, it
remains enabled; if disabled, it remains disabled.
If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11),
ENABLE
If the receiver is already enabled, this command has no effect.
Disables the receiver immediately. Any character being received is lost. The
command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver
operates even though this command is selected. If the receiver is already
disabled, the command has no effect.
When UART1 is in modem mode, if the receiver is disabled while a character is
being received, reception completes before the receiver becomes inactive.
Reserved, do not use.
TC Field (This field selects a single command)
RC (This field selects a single command)
Chapter 14. UART Modules
enables the channel's receiver and forces it into search-for-start-bit state.
Description
Register Descriptions
RECEIVER
14-15