MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 88
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
NOP
NOT
OR
ORI
PEA
PULSE
REMS
REMU
RTS
SATS
Scc
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPF
TST
UNLK
WDDATA
Instruction
execution by setting CSR[UHE].
By default the HALT instruction is a supervisor-level instruction; however, it can be configured to allow user-mode
Instruction Set Summary
Table 2-9 describes supervisor-level instructions.
2-22
none
Dx
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
<ea-3>y
none
<ea-1>,Dx
<ea-1>,Dx
none
Dx
Dx
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
<ea>x
#<vector>
None
#<data>
<ea>y
Ax
<ea>y
Operand Syntax
Table 2-8. User-Level Instruction Set Summary (Continued)
Unsized
.L
.L
.L
.L
Unsized
.L
.L
Unsized
.L
.B
.L
.L
.L
.L
.L
.L
.W
.B
Unsized
Unsized
.W
.L
.B,.W,.L
Unsized
.B,.W,.L
Operand Size
MCF5407 User’s Manual
Synchronize pipelines; PC + 2 → PC
~ Destination → destination
Source | destination → destination
Immediate data | destination → destination
SP – 4 → SP; Address of <ea> → (SP)
Set PST= 0x4
Dx/<ea>y → Dw {32-bit remainder}
Signed operation
Dx/<ea>y → Dw {32-bit remainder}
Unsigned operation
(SP) → PC; SP + 4 → SP
If CCR.V=1,
then if Dx[31] =0
then 0x80000000 → Dx
else 0x7FFFFFFF→ Dx
else Dx is unchanged
If condition true, then 1s destination;
Else 0s → destination
Destination – source → destination
Destination – source → destination
Destination – immediate data → destination
Destination – immediate data → destination
Destination – source – X → destination
MSW of Dx ←→ LSW of Dx
Set CCR; 1→ Bit 7 of <ea>x
SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; format → (SP);
Vector address → PC
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
Set condition codes
Ax →SP; (SP) → Ax; SP + 4 → SP
<ea>y →DDATA port
Operation
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