MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 433

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-3 shows the type of access as a function of match in the CSCRs and DACRs.
Basic bus operations occur in three clocks, as follows:
18.4.2 Data Transfer Cycle States
The data transfer operation in the MCF5407 is controlled by an on-chip state machine. Each
bus clock cycle is divided into two states. Even states occur when CLKIN is high and odd
states occur when CLKIN is low. The state transition diagram for basic and fast-termination
read and write cycles is shown in Figure 18-4.
1. During the first clock, the address, attributes, and TS are driven. AS is asserted at the
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read,
3. The last clock of the bus cycle uses what would be an idle clock between cycles to
0
1
Multiple
0
1
Multiple
0
1
Multiple
falling edge of the clock to indicate that address and attributes are valid and stable.
the external device provides data and is sampled at the rising edge at the end of the
second bus clock. This data is concurrent with TA, which is also sampled at the
rising clock edge.
During a write, the MCF5407 drives data from the rising clock edge at the end of the
first clock to the rising clock edge at the end of the bus cycle. Wait states can be
added between the first and second clocks by delaying the assertion of TA. TA can
be configured to be generated internally through the DACRs and CSCRs. If TA is
not generated internally, the system must provide it externally.
provide hold time for address, attributes, and write data. Figure 18-6 and
Figure 18-8 show the basic read and write operations.
Number of CSCR Matches
Table 18-3. Accesses by Matches in CSCRs and DACRs
0
0
0
1
1
1
Multiple
Multiple
Multiple
Number of DACR Matches
Chapter 18. Bus Operation
External
Defined by CSCRs
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Type of Access
Data Transfer Operation
18-5