MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 360

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Descriptions
Table 14-13 describes UACRn fields.
14.3.15 UART Interrupt Status/Mask Registers
The UART interrupt status registers (UISRn), Figure 14-18, provide status for all potential
interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and
UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the
state of the corresponding UISRn bit has no effect on the output.
Table 14-14 describes UISRn and UIMRn fields.
14-18
7–1
0
Address
Address
Bits
Reset
Reset
Field
Field
R/W
R/W
Name
IEC
(UISRn/UIMRn)
—
Figure 14-18. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
COS
7
7
Reserved, should be cleared.
Input enable control. This bit is not used in modem mode.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
transition on the CTS input (if UIMRn[COS] = 1).
Figure 14-17. UART Auxiliary Control Register (UACRn)
MBAR + 0x1D4 (UISR0), 0x214 (UISR1); MBAR + 0x1D4 (UIMR0), 0x214 (UIMR1)
6
Table 14-13. UACRn Field Descriptions
MBAR + 0x1D0 (UACR0), 0x210 (UACR1)
MCF5407 User’s Manual
—
NOTE:
—
0000_0000
0000_0000
Read only
Write only
Description
3
DB
2
FFULL/RxRDY
1
1
TxRDY
IEC
0
0