MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 450
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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SIZ[1:0], TM[2:0]
General Operation of External Master Transfers
External master transfers that use the MCF5407 to drive memory control signals and TA
are like normal MCF5407 transfers. Figure 18-24 shows timing for basic back-to-back bus
cycles during an external master transfer.
R/W is asserted high for reads and low for writes; otherwise, the transfers are the same. In
Figure 18-24, the MCF5407 chip select’s internal transfer acknowledge is enabled and the
MCF5407 drives TA as an output after a programmed number of wait states.
18-22
A[31:0], TT[1:0]
• For the MCF5407 to assert a CSx during external master accesses, CSMRn[AM]
• To enable DRAM control signals during external master accesses, DCMRn[AM]
• During external master bus cycles, either TS or AS (but not both) should be driven
HOLDREQ
BE/BWE
1
2
BG, BD
Depending on programming, these signals may or may not be driven by the processor.
This signal is driven by the processor for an external master transfer.
D[31:0]
must be set. External master hits use the corresponding CSCRn settings for
auto-acknowledge, byte enables, and wait states. See Section 10.4.1.3, “Chip-Select
Control Registers (CSCR0–CSCR7).”
must be set.
to the MCF5407. Driving both during a bus cycle causes indeterminate results.
CLKIN
CS
BR
R/W
TA
TIP
AS
TS
1
1
1
2
2
Figure 18-24. Basic No-Wait-State External Master Access
C1
C2
C3
MCF5407 User’s Manual
C4
C5
External Master
C6
C7
C8
C9
C10
C11
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