MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 436

IC MPU 32B 220MHZ COLDF 208-FQFP

MCF5407CAI220

Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Datasheets

Specifications of MCF5407CAI220

Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
SIZ[1:0], A[31:0]
Data Transfer Operation
Note the following characteristics of a basic read:
States are described in Table 18-4.
18.4.4 Write Cycle
During a write cycle, the MCF5407 sends data to memory or to a peripheral device. The
write cycle flowchart is shown in Figure 18-7.
TT[1:0], TM[2:0]
18-8
• In S3, data is made available by the external device on the falling edge of CLKIN
• In S4, the external device can stop driving data after the rising edge of CLKIN.
• For a read cycle, the external device stops driving data between S4 and S5.
BEx, OE
AS, CSx
D[31:0]
and is sampled on the rising edge of CLKIN with TA asserted.
However, data could be driven up to S5.
CLKIN
R/W
TIP
TS
TA
termination. TA assertion should look the same in either case.
Figure 18-6. Basic Read Bus Cycle
S0
MCF5407 User’s Manual
S1
S2
S3
Read
S4
S5

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